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iverilog - Icarus Verilog is a verilog compiler and simulator

Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.

License:	GPL	Group:	Applications/Engineering
URL:	http://www.icarus.com/eda/verilog/index.html

Packages

Name	Version	Release	Type	Size	Built
iverilog	0.9.20070608	1.el5	src	1.53 MiB	Mon Jul 30 11:33:35 2007

Changelog

* Sun Jun 10 22:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070608-1

- new snapshot release upstream.

* Mon Apr 23 22:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070421-1

- new snapshot release upstream.

* Tue Feb 27 22:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070227-1

- new snapshoot release.

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